1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for performing result normalization in a floating-point processor. Still more particularly, the present invention relates to a leading-zero/one anticipator in a floating-point processor.
2. Description of the Prior Art
According to the IEEE 754 standard, floating-point numbers are represented by three elements, namely, a binary sign bit, a binary encoded exponent, and a binary encoded mantissa. In a normalized floating-point number, the exponent is that which ensures the first digit of the mantissa is a logical one (except for special cases such as zero, infinities, and unrepresentable numbers). During a normalized floating-point addition, one of the mantissas of the addend and adder is shifted and the exponent is incremented or decremented until the exponents for both the addend and adder are equal. This shifting process is known as alignment. Once aligned, the mantissas of the addend and adder are added or subtracted depending upon the signs of the addend and adder as well as the type of operation (either addition or substraction) to be performed. Once the result (either sum or difference) is formed, the sign of the resulting mantissa is examined. If the sign of the result is negative, the boolean complement of the result is initially formed, and the sign is then complemented. In order to convert the result to a normalized form, the exponent of the result is decremented and the mantissa of the result is left-shifted until the leading digit of the mantissa is a logical one (in absence of exceptional conditions such as those mentioned supra).
The process of removing leading zeros or leading ones from a respective positive or negative output of a floating-point adder is known as normalization. In the prior art, the process of sign determination is typically accomplished by the floating-point adder. Because it is not obvious a priori whether the result from the floating-point adder will be positive or negative, it is necessary to perform both leading-zero and leading-one analysis until the result is finally available so that a proper normalization shift amount can be selected based upon the sign of the result. Hence, the sign determination process can be the most critical path of a, floating-point adder. In lieu of a floating-point adder, a full-precision leading-zero anticipators (LZAs) (or leading-zero predictors) may be utilized to directly determine the sign such that the performance of the normalization process can be improved. The present disclosure describes an improve LZA for performing sign determination.
In accordance with a preferred embodiment of the present invention, an apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.